A SerDes (serializer/deserializer) is the electrical lane under every Ethernet port: it converts the digital bits of the switch or NIC into high-speed analog signals and back again. A port speed is simply the number of lanes multiplied by the rate of each lane, so every time the lane rate doubles, the whole ladder of port speeds above it doubles too. Today’s lane is 224 Gbps PAM4. The next lane, 448 Gbps SerDes, is already in standards work, and it will carry the 3.2T and 6.4T port generations that follow 1.6T.
Why Do Port Speeds Double?
It depends on which layer of the stack you build, but the mechanism is common: every port-speed generation has ridden a lane-rate doubling, and the transitions have compressed as AI demand accelerates. The 28G-to-56G lane transition brought 100G ports; a 50 Gbps-per-lane SerDes announced in 2017 carried the market to 400G ports; 112G lanes carried 800G; and today’s 224G PAM4 lanes are the math behind 1.6T ports and 3.2T-class parts. We published in early 2018 that 200G, 400G and 800G would all ship within five years, and the projection held (see the 2018 press release and What Are 400G, 800G and 1.6T Ports?).
History rhymes: 100 Gbps revenue passed 10 Gbps revenue for the first time in 2Q18, and each later transition has compressed the window between speeds. The industry now ships more networking capacity in a single quarter than it shipped in the entire prior year, and multiple speed transitions running at once drive demand for more DSPs (see AI/ML and Multiple Speed Transitions Driving Need for More DSPs).
What Do 224G Lanes Enable Today?
As of October 2026, 224G PAM4 lanes are in volume under 1.6T ports, with early shipments occurring in 2025, and they are the foundation of the 102.4 Tbps switch platforms emerging in 2H 2026. The same lane math appears inside the server: PCIe moved from Gen 4 at 16 Gbps per lane toward Gen 6 at 64 Gbps per lane, which shrank the usable copper trace from about eight inches to under four and pulled retimers into every AI rack (see PCIe Retimers Market to Surge Driven by AI/ML Computing and What Is a Retimer?). Chip vendors are already staging 3.2T parts on 16 lanes of 224G PAM4 for XPU-to-XPU scale-up links (see Marvell Doubles Down on the AI Memory Wall and the Wires Around It).
What Is 448G SerDes?
448 Gbps SerDes is the next doubling of the electrical lane: two 224 Gbps lanes’ worth of throughput on one lane. It is the first SERDES speed to be developed after the AI inflection, and it is in standards work now at the OIF, which held a dedicated 448 Gbps workshop on the topic (see our notes from the OIF’s 448 Gbps workshop). The lane matters because everything above it inherits the math: with 448G lanes, a 64-lane device reaches 25.6 Tbps of raw electrical capacity toward 6.4T-class ports and beyond-102.4T switch silicon.
When Will 448G Arrive?
It depends on the product layer you care about. Switch vendors plan silicon roadmaps around it; optics and AEC vendors plan modules and cables; server and NIC vendors plan the lanes inside the rack. What we can say from our published cadence research: the transition windows are compressing, the 1.6T ramp builds through 2026 and 2027 alongside 102.4T switch silicon, and 3.2T-class parts are already sampling (see 1.6 Terabit Ethernet Will Drive the Next-Generation AI/ML Wave). The standards process at the OIF is the gate through which every 448G product must pass, which is why we covered the workshop in detail.
How Was This Calculated?
The figures in this Explainer come from 650 Group’s published quarterly research on data center switching, port shipments and interconnect components, which track speeds, lanes and vendor roadmaps each quarter. Each figure links to its publication, and the full catalog is on our research reports page.
What to read next: What Are 400G, 800G and 1.6T Ports? for the port-speed ladder, What Is Merchant Silicon? for the switch silicon economics, and our data center category for quarterly updates.