First Delivery of Silicon Indicates Technology Innovation Cycles are Accelerating
The innovation and product cycles for Cloud infrastructure continue to push the limits of all technologies as Hyperscalers push AI to 1M XPU clusters and squeeze out efficiencies in order to scale power. The push towards AI will fundamentally change most industries in the world, and the industry can’t get there if it doesn’t have enough power or enough interconnect to support this new AI workload. 2nm silicon helps drive towards both these key factors and innovates in new areas to unlock the AI workload in ways that previous generations of silicon could not.
2nm
In early 2024, TSMC provided updates as to when it would reach high volume 2nm (N2) production and targeted 2H25. In December of 2024, TSMC revealed additional details on 2nm. The company highlighted power improvements in the 20-35% range and performance improvements of around 15% compared to the 3nm process. TSMC also highlighted several technology improvements that we viewed as very bullish for interconnect to unleash a significant amount of die-to-die and chip-to-chip bandwidth. At an industry level, we view what TSMC is doing as setting the stage for high-speed photonics interconnects and giving semiconductor companies the tools to get there.
3D and Bi-Directional Technology Increases Bandwidth Significantly
As we begin to see 2nm products, we will continue to see advancements in I/O. Marvell this week announced it has received its first silicon produced on TSMC’s 2nm process. The component is a 6.4Gbits/second bi-directional 3D I/O optimized for stacking silicon die inside chiplets. Think of vertical I/O as the elevator shaft for 2.5D, 3D and 3.5D chiplets: a more robust I/O means more cores and capabilities can ultimately be integrated in the same package. Additionally, skipping unidirectional and going to bidirectional, the amount of bandwidth entering/exiting a chip can increase significantly. This is critical as the beachhead on a chip is often a limiting factor to how much processing you can do in an ASIC. Bi-directional opens up 2nm chips to significant increases in speed.
Broad Portfolio of Products at 2nm
Marvell’s approach of pushing multiple chips through at the same time allows for the coring IP building blocks to be proven out more rapidly. For example, the SERDES for a transceiver can then be reused for the Ethernet Switch ASIC and the XPU. Parallel tracks and building blocks lower the cost to customers, decrease risk to the supplier, and provide a better set of products. We view the scale and diversity of ASICs as key in the 3nm->2nm transition.
Markets Need 2nm to Support Next AI Wave
The agent -aka Agentic- wave for AI will require over $1T in infrastructure spend and push data centers, power grids, and almost all supporting infrastructure to the extremes of what they can support. 2nm products help by driving down the power of solutions. At the same time, much of the new work done at an industry level to support higher interconnect efficiency begins to show up in 2nm. As we change the way we process general workloads to accelerated workloads, we can expect the entire interconnect to change significantly. New designs, like those mentioned above, will allow considerably more memory per XPU (larger models and better user experience) and significant improvements in scale-up (NVLink, UALink, PCIe, Ethernet), scale-out (Ethernet, InfiniBand), and front-end (Ethernet) networks.