Microsoft open sources compression chip design at ocp


We witnessed two significant OCP Summit announcements:

a) open sourcing of semiconductor design
b) improved server system security.

First, Microsoft announced a new compression standard called Project Zipline. The intellectual property for this compression is being made available as open source Verilog (RTL), which will allow others to program semiconductors like FGGAs. The claim is that Project Zipline outperforms existing compression by more than 20%.  This is the first semiconductor design member contribution.

Second, and continuing a theme started at last year’s OCP show, Microsoft announced improvements to Project Cerebus, which is a systems level design and specification to improve server security. Last year, the project addressed boot time security for the CPU. This year’s announcement addresses other subsystems associated with servers, such as accelerators, storage and NICs. We see this project as a reaction to recent concerns of data center hardware compromises that came to light in the public eye over the last couple years.